1. Field of the Invention
This present invention is generally directed to the field of semiconductor processing, and, more particularly, to a method of reducing oxidation of metal structures using ion implantation, and a device formed by performing such a method.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., memory cells, transistors, etc. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical semiconductor device to increase the overall speed of the device, as well as that of integrated circuit devices incorporating such semiconductor devices.
In modem integrated circuits, millions of very small semiconductor devices, e.g., transistors, memory cells, resistors, capacitors, etc., are formed above a semiconducting substrate, such as silicon. To produce a working integrated circuit, all of these various semiconductor devices must be electrically coupled together. This is typically accomplished by a complex arrangement of conductive wiring, e.g., conductive lines and conductive plugs, that are formed in multiple layers of insulating material formed above the substrate. Historically, such conductive wiring patterns have been made from a variety of materials, such as aluminum.
However, as device dimensions continue to shrink, and as the desire for greater performance, e.g., faster operating speeds, has increased, copper has become more popular as the material for the conductive interconnections, i.e., conductive lines and vias, in modern integrated circuit devices. This is due primarily to the higher electrical conductivity of copper as compared to the electrical conductivity of other materials used for such wiring patterns, e.g., aluminum.
Typically, the copper wiring patterns may be formed by performing known single or dual damascene processing techniques. Normally, the conductive lines and plugs for an integrated circuit device are formed in multiple layers of insulating material formed above the substrate. For example, a modern complex integrated circuit device may have four or more levels of these conductive lines and plugs that are connected together such that the circuit may function in its intended manner.
FIGS. 1A-1B depict one illustrative example of an illustrative prior art technique for forming such conductive lines and plugs in a layer of insulating material. As shown in FIG. 1A, a plurality of conductive metal structures 12 are positioned in a first layer of insulating material 10. The first layer of insulating material 10 is intended to be representative in nature in that it may be formed at any location above a semiconducting substrate. The first layer of insulating material 10 may be comprised of a variety of materials, such as silicon dioxide, boron phosphosilicate glass (BPSG), a so-called low-k dielectric, etc. The conductive metal structure 12 may be comprised of a variety of materials, such as copper. In the case where the conductive metal structures 12 are comprised of copper, they may be formed in the first insulating layer 10 using known single or dual damascene techniques.
Thereafter, a diffusion barrier layer 14 is deposited above the first insulating layer 10 and the conductive metal structures 12. The diffusion barrier layer 14 may be comprised of a variety of materials, such as silicon carbide (SiC) or silicon nitride (SiN). As shown in FIG. 1B, a second layer of insulating material 16 is then formed above the diffusion barrier layer 14. The second layer of insulating material 16 may be comprised of the same materials as that of the first layer of insulating material 10. Next, a plurality of openings 18 are formed in the second layer of insulating material 16 and the diffusion barrier layer 14 using one or more known etching processes. A plurality of conductive metal structures 12 are then formed in the openings 18. This process is continued until such time as all of the desired levels of wiring are completed.
The diffusion barrier layer 14 is provided to reduce or prevent oxidation of the upper surface 13 of the conductive metal structures 12 positioned in the first layer of insulating material 10 during the subsequent formation of the second layer of insulating material 16. That is, the second layer of insulating material 16 is normally formed in an oxygen environment at a temperature in excess of 150-200xc2x0 C. If the diffusion barrier layer 14 were not present, the upper surface 13 of the conductive metal structures 12 would oxidize to some degree. Such oxidation would be undesirable for a variety of reasons, e.g., it would increase the resistance of the conductive metal structure 12. However, the use of the diffusion barrier layer 14 to address this problem effectively increases the dielectric constant of the insulating materials positioned around the conductive metal structures 12. That is, a typical diffusion barrier layer 14 may be comprised of a material having a dielectric constant that ranges from approximately 4-8. As a result of the use of the diffusion barrier layer 14, the overall capacitance of the device may be increased thereby tending to produce a slower operating device.
The present invention is directed to a method that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to various methods of reducing oxidation of metal structures using ion implantation, and an integrated circuit device formed by such methods. In one illustrative embodiment, the method comprises providing a semiconducting substrate having a first layer of insulating material formed thereabove, the first layer of insulating material having at least one conductive structure positioned therein, and performing an ion implant process to implant ions into at least one conductive structure. In other embodiments, the method further comprises forming a second layer of insulating material above the first layer of insulating material and at least one conductive structure. In even further embodiments, ions are selectively implanted only into the conductive metal structure. In an additional embodiment, the ions are implanted into both the first layer of insulating material and into the conductive metal structure.
In one illustrative embodiment, the integrated circuit device comprises a first layer of insulating material positioned above a semiconducting substrate and at least one conductive metal structure positioned in the first layer of insulating material, wherein the conductive metal structure has a doped region formed therein adjacent a first surface of the conductive metal structure. In a further embodiment, a second layer of insulating material is positioned above the first layer of insulating material and the conductive metal structure.